On the interpretation of MOS impedance data in both series and parallel circuit topologies

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dc.contributor.authorCaruso, Enrico
dc.contributor.authorLin, Jun
dc.contributor.authorMonaghan, Scott
dc.contributor.authorCherkaoui, Karim
dc.contributor.authorFloyd, Liam
dc.contributor.authorGity, Farzan
dc.contributor.authorPalestri, P.
dc.contributor.authorEsseni, D.
dc.contributor.authorSelmi, L.
dc.contributor.authorHurley, Paul K.
dc.date.accessioned2022-07-26T12:29:36Z
dc.date.available2022-07-26T12:29:36Z
dc.date.issued2021-09
dc.date.updated2022-07-22T11:10:23Z
dc.description.abstractThe ac impedance/admittance modulus (Z, Y) and phase angle (θ) of the MOS structure at a given voltage is typically represented via its frequency-dependent capacitive (C) and conductive (G) elements according to either a series or a parallel equivalent circuit. The resulting C (ω,V) and G (ω,V) data are used to characterize the basic MOS structure and its electrically active defect parameters [1]. The objective of this contribution is to investigate the impact and significance of using both series and parallel equivalent circuit representations for the case of an MOS system in inversion. Our study comprises a mathematical analysis of the equivalent circuit models, physics based impedance simulations and experimental data for Si and InGaAs MOS structures.en
dc.description.statusPeer revieweden
dc.description.versionAccepted Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationCaruso, E., Lin, J., Monaghan, S., Cherkaoui, K., Floyd, L., Gity, F., Palestri, P., Esseni, D., Selmi, L. and Hurley, P. K. (2021) 'On the interpretation of MOS impedance data in both series and parallel circuit topologies', 7th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS'2021), Caen, France, 1-3 September.en
dc.identifier.endpage2en
dc.identifier.startpage1en
dc.identifier.urihttps://hdl.handle.net/10468/13405
dc.language.isoenen
dc.relation.ispartof7th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS'2021), Caen, France, 1-3 September 2021
dc.rights© 2021, the Authors.en
dc.subjectMOS structureen
dc.subjectCircuiten
dc.titleOn the interpretation of MOS impedance data in both series and parallel circuit topologiesen
dc.typeConference itemen
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