A 2-MS/s, 11.22 ENOB, extended input range SAR ADC with improved DNL and offset calculation

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dc.contributor.authorAsghar, Sohail
dc.contributor.authorAfridi, Sohaib Saadat
dc.contributor.authorPillai, Anu
dc.contributor.authorSchuler, Anita
dc.contributor.authorde la Rosa José
dc.contributor.authorO'Connell, Ivan
dc.contributor.funderEnterprise Irelanden
dc.contributor.funderEuropean Regional Development Funden
dc.contributor.funderJunta de Andalucíaen
dc.date.accessioned2020-02-18T12:16:22Z
dc.date.available2020-02-18T12:16:22Z
dc.date.issued2018-11
dc.date.updated2020-02-18T12:06:05Z
dc.description.abstractA 12-bit successive approximation register analog-to-digital converter (ADC) with extended input range is presented. Employing an input sampling scaling technique, the presented ADC can digitize the signals with an input range of 3.2 V pp-d (±1.33 V REF ). The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The chip has been designed and implemented in a 0.13-μm CMOS process and demonstrates the state-of-the-art performance, featuring an SNDR of 69.3 dB and the SFDR of 79 dB without requiring any calibration. Total power consumption of the ADC is 0.9 mW, with a measured differential non-linearity of 1.2/-1.0 LSB and INL of 2.3/-2.2 LSB.en
dc.description.sponsorshipEnterprise Ireland (with MCCI under the Innovation Partnership Programme under Grant IP/2013/0257); Junta de Andalucía (Spanish & Andalusian Government (with support from European RDF under Contract TEC2016-75151-C3-3-R and Contract P12-TIC-1481))en
dc.description.statusPeer revieweden
dc.description.versionAccepted Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationAsghar, S., Afridi, S. S., Pillai, A., Schuler, A., Rosa, J. M. d. l. and O’Connell, I. (2018) 'A 2-MS/s, 11.22 ENOB, Extended Input Range SAR ADC With Improved DNL and Offset Calculation', IEEE Transactions on Circuits and Systems I: Regular Papers, 65(11), pp. 3628-3638. doi: 10.1109/TCSI.2018.2852761en
dc.identifier.doi10.1109/TCSI.2018.2852761en
dc.identifier.endpage3638en
dc.identifier.issn1558-0806
dc.identifier.issued11en
dc.identifier.journaltitleIEEE Transactions On Circuits And Systems I: Regular Papersen
dc.identifier.startpage3628en
dc.identifier.urihttps://hdl.handle.net/10468/9657
dc.identifier.volume65en
dc.language.isoenen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.relation.urihttps://ieeexplore.ieee.org/document/8439041
dc.rights© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.en
dc.subjectAnalogue-digital conversionen
dc.subjectCMOS integrated circuitsen
dc.subjectComparators (circuits)en
dc.subjectIntegrated circuit designen
dc.subjectComparator offset compensation techniqueen
dc.subjectOffset calculationen
dc.subjectInput sampling scaling techniqueen
dc.subjectSuccessive approximation register analog-to-digital converteren
dc.subjectExtended Input Range SAR ADCen
dc.subjectDNLen
dc.subjectCMOS processen
dc.subjectNoise figure 69.3 dBen
dc.subjectNoise figure 79.0 dBen
dc.subjectPower 0.9 mWen
dc.subjectSize 0.13 mumen
dc.subjectCapacitorsen
dc.subjectLinearityen
dc.subjectParasitic capacitanceen
dc.subjectCalibrationen
dc.subjectMonitoringen
dc.subjectAnalog-to-digital convertersen
dc.subjectSARen
dc.subjectComparator offseten
dc.subjectCapacitor segmentationen
dc.subjectFeedback control systemen
dc.titleA 2-MS/s, 11.22 ENOB, extended input range SAR ADC with improved DNL and offset calculationen
dc.typeArticle (peer-reviewed)en
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