Analysis and design of low phase noise CMOS oscillator circuit topologies

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dc.check.date2022-06-21T10:22:06Z
dc.check.embargoformatBoth hard copy thesis and e-thesisen
dc.check.entireThesisEntire Thesis Restricted
dc.check.infoRestricted to everyone for five yearsen
dc.check.opt-outNoen
dc.check.reasonThis thesis is due for publication or the author is actively seeking to publish this materialen
dc.contributor.advisorPepe, Domenicoen
dc.contributor.advisorZito, Domenicoen
dc.contributor.authorChlis, Ilias
dc.contributor.funderScience Foundation Irelanden
dc.date.accessioned2017-06-22T10:22:06Z
dc.date.issued2016
dc.date.submitted2016
dc.description.abstractThe research activity carried out during the PhD is focused on the study, analysis and design of millimeter-wave integrated oscillator circuits for high-speed wireless communications. In Chapter 1 comparative analyses of phase noise (PN) in Hartley, Colpitts and commonsource cross-coupled differential pair LC oscillator topologies are carried out under common conditions in 28 nm CMOS technology. The impulse sensitivity function (ISF) is used to carry out both qualitative and quantitative analyses of the phase noise exhibited by each circuit component in each circuit topology with oscillation frequency ranging from 1 to 100 GHz. The comparative analyses show the existence of four distinct frequency regions in which the three oscillator topologies rank unevenly in terms of best phase noise performance, due to the combined effects of device noise and circuit node sensitivity. Moreover, the analyses show that there is no superior oscillator topology in the absolute sense, but that the identification of the best circuit topology with respect to phase noise is strictly related to the operating frequency range. In Chapter 2 comparative phase noise analyses of common-source cross-coupled pair, Colpitts, Hartley and Armstrong differential oscillator circuit topologies, designed in 28 nm bulk CMOS technology in a set of common conditions for operating frequencies in the range from 1 to 100 GHz, are carried out in order to identify their relative performance. The impulse sensitivity function is used to carry out qualitative and quantitative analyses of the noise contributions exhibited by each circuit component in each topology, allowing an understanding of their impact on phase noise. The comparative analyses show the existence of five distinct frequency regions in which the four topologies rank unevenly in terms of best phase noise performance. Moreover, the results obtained from the impulse sensitivity function show the impact of flicker noise contribution as the major effect leading to phase noise degradation in nano-scale CMOS LC oscillators. Chapter 3 reports a phase noise analysis in a differential Armstrong oscillator circuit topology in CMOS technology. The analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations for oscillation frequencies of 1, 10 and 100 GHz. The analysis captures well the phase noise of the oscillator topology and shows the impact of flicker noise contribution as the major effect leading to phase noise degradation in nano-scale CMOS LC oscillators. Chapter 4 reports the analyses of three techniques for phase noise reduction in the CMOS Colpitts oscillator circuit topology. Namely, the three techniques are: inductive degeneration, noise filter, and optimum current density. The design of the circuit topology is carried out in 28 nm bulk CMOS technology. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. Moreover, the theoretical analyses of the three techniques are carried out and verified by means of circuit simulations within a commercial design environment. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. The results obtained for the optimum bias current density technique applied to a Colpitts oscillator circuit topology incorporating either inductive degeneration or noise filter, show the existence of an optimum bias current density for minimum phase noise. Overall, the analyses show that, with respect to the reference values obtained in Chapter 2, the adoption of these techniques may lead to a potential phase noise reduction up to 19 dB and 17 dB at a 1 MHz frequency offset for the oscillation frequencies of 10 GHz and 100 GHz respectively. Chapter 5 reports the analyses of the three techniques discussed in Chapter 4, applied to the CMOS Hartley oscillator circuit topology. The design of the circuit topology is carried out in 28 nm bulk CMOS technology. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. Moreover, the theoretical analyses of the three techniques are carried out and verified by means of circuit simulations. As in the case of the Colpitts topology, the results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. The results obtained for the optimum bias current density technique applied to a Hartley oscillator circuit topology incorporating either inductive degeneration or noise filter, show the existence of an optimum bias current density for minimum phase noise. Overall, wih respect to the reference values obtained in Chapter 2, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 17 dB and 16 dB at a 1 MHz frequency offset for the oscillation frequencies of 10 GHz and 100 GHz respectively, with respect to the traditional Hartley topology. Finally, Chapter 6 reports the design of an advanced solution, adopting the techniques discussed in Chapters 4 and 5. The voltage-controlled oscillator (VCO) topology can be tuned from 58.1 GHz to 63.3 GHz. From periodic steady state (PSS) and periodic noise (Pnoise) SpectreRF simulations the best phase noise performance is observed for f0=63.3 GHz, and amounts to -100.2 dBc/Hz at a 1 MHz frequency offset from the oscillation frequency, for a power consumption of 13.6 mW. This corresponds to a figure of merit (FOM) of 185 dB.en
dc.description.sponsorshipScience Foundation Ireland (Grants 11/RFP/ECE3325 & 07/SK/I1258)en
dc.description.statusNot peer revieweden
dc.description.versionAccepted Version
dc.format.mimetypeapplication/pdfen
dc.identifier.citationChlis, I. 2016. Analysis and design of low phase noise CMOS oscillator circuit topologies. PhD Thesis, University College Cork.en
dc.identifier.endpage131en
dc.identifier.urihttps://hdl.handle.net/10468/4146
dc.languageEnglishen
dc.language.isoenen
dc.publisherUniversity College Corken
dc.rights© 2016, Ilias Chlis.en
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/en
dc.subjectColpittsen
dc.subjectHartleyen
dc.subjectVCOen
dc.subjectInductive degenerationen
dc.subjectOptimum current densityen
dc.subjectNoise filteren
dc.subjectOscillator analysisen
dc.subjectPhase noiseen
dc.thesis.opt-outfalse
dc.titleAnalysis and design of low phase noise CMOS oscillator circuit topologiesen
dc.typeDoctoral thesisen
dc.type.qualificationlevelDoctoralen
dc.type.qualificationnamePHD (Engineering)en
ucc.workflow.supervisord.zito@ucc.ie
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