A divider controller for optimized fractional-N frequency synthesizer spectral performance in the presence of loop nonlinearities
dc.check.date | 2024-01-15T12:56:18Z | |
dc.check.embargoformat | Apply the embargo to the hard bound thesis (If you have not submitted an e-thesis and want to embargo the hard bound thesis in UCC Library) | en |
dc.check.entireThesis | Entire Thesis Restricted | |
dc.check.info | Restricted to everyone for five years | en |
dc.check.opt-out | Yes | en |
dc.check.reason | Releasing this thesis would cause substantial prejudice to the commercial interests of University College Cork | en |
dc.contributor.advisor | Kennedy, Michael Peter | en |
dc.contributor.advisor | O'Connell, Ivan | en |
dc.contributor.author | Donnelly, Yann | |
dc.contributor.funder | Irish Research Council | en |
dc.contributor.funder | Science Foundation Ireland | en |
dc.date.accessioned | 2019-01-16T12:56:18Z | |
dc.date.issued | 2018 | |
dc.date.submitted | 2018 | |
dc.description.abstract | The fractional-N Phase Lock Loop (PLL) is an essential block in modern radio frequency systems, where it is used primarily for frequency synthesis. The primary feature of the fractional-N PLL is the use of a modulator, the so-called “divider controller”, to control the feedback divider. The arbitrary accuracy of frequency synthesis comes at the cost of phase noise in the output frequency spectrum, in particular spurious frequency components (spurs). When these components appear in the passband of the loop response, they dominate in the overall frequency spectrum. This thesis demonstrates that these spurs occur as a result of the interaction between modulation noise, introduced by the divider controller, and nonlinearities in the PLL. A mechanism is presented describing the generation of these spurs. A semianalytical method of determining the spurs and phase noise resulting from a given choice of divider controller and nonlinearity is presented, requiring only knowledge of the controller’s accumulated output probability mass function and the nonlinearity. A number of candidate divider controllers are studied, and the performance of the Nested Cascaded MASH and MASH-SQ Hybrid are derived. A novel controller is presented, and it is shown that this controller can be used to mitigate the problem through a “spur avoidance” technique. An implementation of this controller is evaluated, and found to offer a worst spur reduction of between 7.0 dB and 19.5 dB compared to a standard MASH-based divider controller, as well as spur reductions of between 15.6 dB and 24.5 dB in the absence of bleed current. The best observed worst spur height of −83.9 dBc is significantly lower than previous reported state-of-the-art. Finally, a hitherto underexplored phenomenon, termed the Wandering Spur, is examined. This phenomenon is shown to be derived from the architecture of the MASH modulator, and an analytical prediction in the MASH 1-1 case is presented. | en |
dc.description.status | Not peer reviewed | en |
dc.description.version | Accepted Version | |
dc.format.mimetype | application/pdf | en |
dc.identifier.citation | Donnelly, Y. 2019. A divider controller for optimized fractional-N frequency synthesizer spectral performance in the presence of loop nonlinearities. PhD Thesis, University College Cork. | en |
dc.identifier.uri | https://hdl.handle.net/10468/7305 | |
dc.language.iso | en | en |
dc.publisher | University College Cork | en |
dc.relation.project | info:eu-repo/grantAgreement/SFI/SFI Research Centres/13/RC/2077/IE/CONNECT: The Centre for Future Networks & Communications/ | en |
dc.relation.project | Irish Research Council (Grant Number GOIPG/2014/14222) | en |
dc.rights | © 2018, Yann Donnelly. | en |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/ | en |
dc.subject | Phase lock loop | en |
dc.subject | Frequency synthesizer | en |
dc.subject | Spurious | en |
dc.subject | Spur | en |
dc.subject | Phase noise | en |
dc.subject | Nonlinearity | en |
dc.subject | Nonideality | en |
dc.subject | Wireless | en |
dc.subject | Radio frequency | en |
dc.thesis.opt-out | true | |
dc.title | A divider controller for optimized fractional-N frequency synthesizer spectral performance in the presence of loop nonlinearities | en |
dc.type | Doctoral thesis | en |
dc.type.qualificationlevel | Doctoral | en |
dc.type.qualificationname | PhD | en |
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