Restriction lift date: 2025-04-23
Design of a low power, 14-bit continuous time delta sigma modulator for IoT radio receiver
Loading...
Files
Date
2018-08-31
Authors
Assom, Ian
Journal Title
Journal ISSN
Volume Title
Publisher
University College Cork
Published Version
Abstract
Analog-to-Digital Converters are a fundamental building block of modern integrated RF radio transceivers. In the receiver signal chain, converting an analog baseband signal to the digital domain can consume a significant proportion of an integrated transceivers power budget. Coupled with this, the demand for flexible, low power, and robust ADCs to meet modern Internet of Things (IoT) wireless communication standards are ever increasing. Due to their oversampling nature, and inherent anti-aliasing filtering properties, Continuous Time Delta Sigma Modulator (CTDSM) ADCs are very well suited for low power IoT radio receiver architectures. However, CTDSM performance can suffer from clock jitter effects and inter-symbol interference (ISI) in the feedback DAC waveform which can significantly reduce SNR at the ADC output. The feedback DACs in CTDSM dictates the overall modulator’s accuracy since any error introduced by this block appears directly at the output. In multibit CTDSMs the DAC mismatch greatly limits the modulator linearity. On the other hand, single bit CTDSMs are inherently linear and more area efficient compared to multibit counterpart, however they require higher order loop filters and oversampling ratio (OSR) to achieve similar performance. Also, variation in the rising and falling times of the DAC pulses in CTDSMs produce ISI. Previous works have shown that employing a Return-to-Zero (RTZ) feedback DAC pulse, the ISI issue can be mitigated at the expense of increasing clock jitter sensitivity. On the other hand, incorporating Finite Impulse Response (FIR) filter in the feedback DAC can reduce the clock jitter sensitivity.
This work will propose a 4th order feedforward, single bit CTDSM with a return-to-zero (RTZ) feedback DAC that achieves state-of-the-art SNR in the presence of significant clock jitter by incorporating a FIR feedback DAC in the feedback path. The proposed single bit design combines the lower ISI sensitivity of the RTZ DAC with the lower jitter sensitivity of FIR DAC to produce a CTDSM suitable for IoT radio receiver and allows for an area efficient design that can meet the strict linearity and SNR requirements of a low power, high performance IoT based receiver architecture. The proposed CTDSM architecture was first modelled and simulated in MATLAB SIMULINK to demonstrate the feasibility of the adopted methodology of addressing DAC non-idealities in CTDSM. Time domain behavioral simulation achieves a peak SNR of 89 dB without circuit thermal noise in presence of 4.2 ps rms jitter at 24 MHz sampling frequency over 250 kHz bandwidth. The circuit-level realization of the CTDSM in 65 nm CMOS process has a simulated power consumption of 1.407 mW from a 1.2 V supply. The Walden figure of merit is FoM_W=0.172pJ\/conv. And the peak SNR of 84.8 dB was achieved under the influence of circuit thermal noise.
Description
Keywords
Continuous time delta sigma modulator , ADC , IoT , Radio receiver , A return-to-zero (RTZ) feedback DAC
Citation
Assom, I. D. 2018. Design of a low power, 14-bit continuous time delta sigma modulator for IoT radio receiver. MRes Thesis, University College Cork.