Bandwidth enhancement to continuous-time input pipeline ADCs

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dc.contributor.authorO'Hare, Daniel
dc.contributor.authorScanlan, Anthony G.
dc.contributor.authorThompson, Eric
dc.contributor.authorMullane, Brendan
dc.contributor.funderEuropean Regional Development Fund
dc.contributor.funderIrish Government
dc.contributor.funderEnterprise Ireland
dc.date.accessioned2018-07-30T10:30:32Z
dc.date.available2018-07-30T10:30:32Z
dc.date.issued2018
dc.description.abstractThis paper presents design analysis and insights for a new continuous-time input pipeline (CTIP) analog-to-digital converter (ADC) architecture that has enhanced bandwidth. An all-pass filter-based analog delay in the signal path allows bandwidth extension to Nyquist signal bandwidths. A resetting integrator gain stage provides a signal path delay helping to increase the bandwidth while reducing the power cost. The noise filtering property of the resetting integrator gain stage preserves the medium resistive input benefit of CTIP ADCs. The resetting integrator allows the architecture to be implemented with a feedforward compensated op-amp using low-voltage CMOS processes. This paper has been verified by simulation results of a CTIP ADC with 1.2-V supply voltage designed in TSMC's 65-nm CMOS technology.en
dc.description.sponsorshipEnterprise Ireland (Innovation Partnership Project IP-2014-0293)en
dc.description.statusPeer revieweden
dc.description.versionAccepted Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationO’Hare, D., Scanlan, A. G., Thompson, E. and Mullane, B. (2018) 'Bandwidth enhancement to continuous-time input pipeline ADCs', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(2), pp. 404-415. doi: 10.1109/TVLSI.2017.2763129en
dc.identifier.doi10.1109/TVLSI.2017.2763129
dc.identifier.endpage415
dc.identifier.issn1063-8210
dc.identifier.issued2
dc.identifier.journaltitleIEEE Transactions on Very Large Scale Integration (VLSI) Systemsen
dc.identifier.startpage404
dc.identifier.urihttps://hdl.handle.net/10468/6522
dc.identifier.volume26
dc.language.isoenen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.relation.urihttps://ieeexplore.ieee.org/document/8091299/
dc.rights© 2017, IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.en
dc.rights.urihttp://www.ieee.org/publications_standards/publications/rights/index.html
dc.subjectAnalog-to-digital conversionen
dc.subjectAntialias filteren
dc.subjectCMOS analog integrated circuitsen
dc.subjectContinuous timeen
dc.subjectPipelineen
dc.titleBandwidth enhancement to continuous-time input pipeline ADCsen
dc.typeArticle (peer-reviewed)en
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