Hardware reduction in digital delta-sigma modulators via error masking - part II: SQ-DDSM

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Hardware reduction in digital delta-sigma modulators via error masking - part II: SQ-DDSM

Ye, Zhipeng; Kennedy, Michael Peter
Date: 2009-02
Copyright: ©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Citation: Ye, Z., Kennedy, M.P., 2009. Hardware reduction in digital delta-sigma modulators via error masking - part II: Sq-DDSM. IEEE Transactions On Circuits and Systems II - Express Briefs, 56 (2), pp.112-116.
Published Version: 10.1109/TCSII.2008.2010188

Abstract:

In this two-part paper, a design methodology for reduced-complexity digital delta-sigma modulators (DDSMs) based on error masking is presented. Rules for selecting the wordlengths of the stages in multistage architectures are elaborated. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation results confirm theoretical predictions. Part I addresses multistage noise-shaping DDSMs, whereas Part II focuses on single-quantizer DDSMs.

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