On the interpretation of MOS impedance data in both series and parallel circuit topologies

Caruso, Enrico; Lin, Jun; Monaghan, Scott; Cherkaoui, Karim; Floyd, Liam; Gity, Farzan; Palestri, P.; Esseni, D.; Selmi, L.; Hurley, Paul K.

On the interpretation of MOS impedance data in both series and parallel circuit topologies

Files

INFOS_2021_Enrico_Caruso_Submitted.pdf(281.34 KB)

Accepted Version

Date

2021-09

Authors

Caruso, Enrico

Lin, Jun

Monaghan, Scott

Cherkaoui, Karim

Floyd, Liam

Gity, Farzan

Palestri, P.

Esseni, D.

Selmi, L.

Hurley, Paul K.

Abstract

The ac impedance/admittance modulus (Z, Y) and phase angle (θ) of the MOS structure at a given voltage is typically represented via its frequency-dependent capacitive (C) and conductive (G) elements according to either a series or a parallel equivalent circuit. The resulting C (ω,V) and G (ω,V) data are used to characterize the basic MOS structure and its electrically active defect parameters [1]. The objective of this contribution is to investigate the impact and significance of using both series and parallel equivalent circuit representations for the case of an MOS system in inversion. Our study comprises a mathematical analysis of the equivalent circuit models, physics based impedance simulations and experimental data for Si and InGaAs MOS structures.

Keywords

MOS structure , Circuit

Citation

Caruso, E., Lin, J., Monaghan, S., Cherkaoui, K., Floyd, L., Gity, F., Palestri, P., Esseni, D., Selmi, L. and Hurley, P. K. (2021) 'On the interpretation of MOS impedance data in both series and parallel circuit topologies', 7th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS'2021), Caen, France, 1-3 September.