Low-temperature conductance oscillations in junctionless nanowire transistors

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Low-temperature conductance oscillations in junctionless nanowire transistors

Park, Jong-Tae; Kim, Jin Young; Lee, Chi-Woo; Colinge, Jean-Pierre
Date: 2010
Copyright: © 2010 American Institute of Physics.This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. The following article appeared in Park, J.-T., Kim, J. Y., Lee, C.-W. and Colinge, J.-P. (2010) 'Low-temperature conductance oscillations in junctionless nanowire transistors', Applied Physics Letters, 97(17), pp. 172101 and may be found at http://aip.scitation.org/doi/abs/10.1063/1.3506899
Related: http://aip.scitation.org/doi/abs/10.1063/1.3506899
Citation: Park, J.-T., Kim, J. Y., Lee, C.-W. and Colinge, J.-P. (2010) 'Low-temperature conductance oscillations in junctionless nanowire transistors', Applied Physics Letters, 97(17), pp. 172101. doi: 10.1063/1.3506899
Published Version: 10.1063/1.3506899

Abstract:

Junctionless nanowire transistors show more marked oscillations conductance oscillations than inversion-mode devices. These oscillations can be observed at higher temperature, drain voltage, and gate voltage than in surface-channel, inversion-mode multigate metal-oxide-semiconductor field-effect devices. Clear oscillations are observed at 77 K at a drain voltage of 100 mV in devices with a 10 x 10 nm(2) cross section. (C) 2010 American Institute of Physics. (doi:10.1063/1.3506899)

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