Simulation of junctionless Si nanowire transistors with 3 nm gate length

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dc.contributor.author Ansari, Lida
dc.contributor.author Feldman, Baruch
dc.contributor.author Fagas, Gíorgos
dc.contributor.author Colinge, Jean-Pierre
dc.contributor.author Greer, James C.
dc.date.accessioned 2017-07-28T11:04:42Z
dc.date.available 2017-07-28T11:04:42Z
dc.date.issued 2010
dc.identifier.citation Ansari, L., Feldman, B., Fagas, G., Colinge, J.-P. and Greer, J. C. (2010) 'Simulation of junctionless Si nanowire transistors with 3 nm gate length', Applied Physics Letters, 97(6), pp. 062105. doi: 10.1063/1.3478012 en
dc.identifier.volume 97
dc.identifier.issued 6
dc.identifier.startpage 1
dc.identifier.endpage 3
dc.identifier.issn 0003-6951
dc.identifier.issn 1077-3118
dc.identifier.uri http://hdl.handle.net/10468/4336
dc.identifier.doi 10.1063/1.3478012
dc.description.abstract Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform proof-of-concept simulations of junctionless gated Si nanowire transistors. Based on first-principles, our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of similar to 1 nm wire diameter and similar to 3 nm gate length, and that the junctionless transistor avoids potentially serious difficulties affecting junctioned channels at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration. (C) 2010 American Institute of Physics. (doi:10.1063/1.3478012) en
dc.description.sponsorship Science Foundation Ireland (SFI Grant No. 06/IN.1/I857) en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher AIP Publishing en
dc.relation.uri http://aip.scitation.org/doi/abs/10.1063/1.3478012
dc.rights © 2010 American Institute of Physics.This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. The following article appeared in Ansari, L., Feldman, B., Fagas, G., Colinge, J.-P. and Greer, J. C. (2010) 'Simulation of junctionless Si nanowire transistors with 3 nm gate length', Applied Physics Letters, 97(6), pp. 062105 and may be found at http://aip.scitation.org/doi/abs/10.1063/1.3478012 en
dc.subject Ab initio calculations en
dc.subject Elemental semiconductors en
dc.subject Nanowires en
dc.subject Silicon en
dc.subject Transistors en
dc.subject Doping en
dc.subject MOSFETs en
dc.subject Density functional theory en
dc.subject Lead en
dc.title Simulation of junctionless Si nanowire transistors with 3 nm gate length en
dc.type Article (peer-reviewed) en
dc.internal.authorcontactother Lida Ansari, Tyndall National Institute, University College Cork, Cork, Ireland +353 (0)21 2346063, Email: lida.ansari@tyndall.ie en
dc.internal.availability Full text available en
dc.description.version Published Version en
dc.internal.wokid WOS:000280940900035
dc.contributor.funder Science Foundation Ireland
dc.description.status Peer reviewed en
dc.identifier.journaltitle Applied Physics Letters en
dc.internal.IRISemailaddress lida.ansari@tyndall.ie en
dc.identifier.articleid 62105


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