Simulation of junctionless Si nanowire transistors with 3 nm gate length

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dc.contributor.authorAnsari, Lida
dc.contributor.authorFeldman, Baruch
dc.contributor.authorFagas, GĂ­orgos
dc.contributor.authorColinge, Jean-Pierre
dc.contributor.authorGreer, James C.
dc.contributor.funderScience Foundation Ireland
dc.date.accessioned2017-07-28T11:04:42Z
dc.date.available2017-07-28T11:04:42Z
dc.date.issued2010
dc.description.abstractInspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform proof-of-concept simulations of junctionless gated Si nanowire transistors. Based on first-principles, our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of similar to 1 nm wire diameter and similar to 3 nm gate length, and that the junctionless transistor avoids potentially serious difficulties affecting junctioned channels at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration. (C) 2010 American Institute of Physics. (doi:10.1063/1.3478012)en
dc.description.sponsorshipScience Foundation Ireland (SFI Grant No. 06/IN.1/I857)en
dc.description.statusPeer revieweden
dc.description.versionPublished Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.articleid62105
dc.identifier.citationAnsari, L., Feldman, B., Fagas, G., Colinge, J.-P. and Greer, J. C. (2010) 'Simulation of junctionless Si nanowire transistors with 3 nm gate length', Applied Physics Letters, 97(6), pp. 062105. doi: 10.1063/1.3478012en
dc.identifier.doi10.1063/1.3478012
dc.identifier.endpage3
dc.identifier.issn0003-6951
dc.identifier.issn1077-3118
dc.identifier.issued6
dc.identifier.journaltitleApplied Physics Lettersen
dc.identifier.startpage1
dc.identifier.urihttps://hdl.handle.net/10468/4336
dc.identifier.volume97
dc.language.isoenen
dc.publisherAIP Publishingen
dc.relation.urihttp://aip.scitation.org/doi/abs/10.1063/1.3478012
dc.rights© 2010 American Institute of Physics.This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. The following article appeared in Ansari, L., Feldman, B., Fagas, G., Colinge, J.-P. and Greer, J. C. (2010) 'Simulation of junctionless Si nanowire transistors with 3 nm gate length', Applied Physics Letters, 97(6), pp. 062105 and may be found at http://aip.scitation.org/doi/abs/10.1063/1.3478012en
dc.subjectAb initio calculationsen
dc.subjectElemental semiconductorsen
dc.subjectNanowiresen
dc.subjectSiliconen
dc.subjectTransistorsen
dc.subjectDopingen
dc.subjectMOSFETsen
dc.subjectDensity functional theoryen
dc.subjectLeaden
dc.titleSimulation of junctionless Si nanowire transistors with 3 nm gate lengthen
dc.typeArticle (peer-reviewed)en
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