Simulation of junctionless Si nanowire transistors with 3 nm gate length

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Date
2010
Authors
Ansari, Lida
Feldman, Baruch
Fagas, Gíorgos
Colinge, Jean-Pierre
Greer, James C.
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AIP Publishing
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Abstract
Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform proof-of-concept simulations of junctionless gated Si nanowire transistors. Based on first-principles, our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of similar to 1 nm wire diameter and similar to 3 nm gate length, and that the junctionless transistor avoids potentially serious difficulties affecting junctioned channels at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration. (C) 2010 American Institute of Physics. (doi:10.1063/1.3478012)
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Ab initio calculations , Elemental semiconductors , Nanowires , Silicon , Transistors , Doping , MOSFETs , Density functional theory , Lead
Citation
Ansari, L., Feldman, B., Fagas, G., Colinge, J.-P. and Greer, J. C. (2010) 'Simulation of junctionless Si nanowire transistors with 3 nm gate length', Applied Physics Letters, 97(6), pp. 062105. doi: 10.1063/1.3478012
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© 2010 American Institute of Physics.This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. The following article appeared in Ansari, L., Feldman, B., Fagas, G., Colinge, J.-P. and Greer, J. C. (2010) 'Simulation of junctionless Si nanowire transistors with 3 nm gate length', Applied Physics Letters, 97(6), pp. 062105 and may be found at http://aip.scitation.org/doi/abs/10.1063/1.3478012