Characterizing stress in ultrathin silicon wafers

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Characterizing stress in ultrathin silicon wafers

Paul, Indrajit; Majeed, Bivragh; Razeeb, Kafil M.; Barton, John
Date: 2006
Copyright: © 2006 American Institute of Physics.This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. The following article appeared in Paul, I., Majeed, B., Razeeb, K. M. and Barton, J. (2006) 'Characterizing stress in ultrathin silicon wafers', Applied Physics Letters, 89(7), pp. 073506 and may be found at http://aip.scitation.org/doi/abs/10.1063/1.2336212
Related: http://aip.scitation.org/doi/abs/10.1063/1.2336212
Citation: Paul, I., Majeed, B., Razeeb, K. M. and Barton, J. (2006) 'Characterizing stress in ultrathin silicon wafers', Applied Physics Letters, 89(7), pp. 073506.
Published Version: 10.1063/1.2336212

Abstract:

The aim of this letter is to calculate the mechanical grinding induced bow and stress in ultrathin silicon wafers. The reverse leakage current of a p-n junction diode fabricated on a 4 in. silicon wafer was measured for wafers thinned to various thicknesses. A correlation with the residual stress was obtained through band gap narrowing effect. The analytical results were compared with experimental bow measurements using a laser profiler. The bow in 50 mu m thick wafer was found to be less than 2 mm using the current grinding process. (c) 2006 American Institute of Physics. (DOI:10.1063/1.2336212)

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