Properties of latent interface-trap buildup in irradiated metal-oxide-semiconductor transistors determined by switched bias isothermal annealing experiments

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dc.contributor.author Jaksic, Aleksandar B.
dc.contributor.author Pejovic, M. M.
dc.contributor.author Ristic, G. S.
dc.date.accessioned 2017-07-28T13:29:55Z
dc.date.available 2017-07-28T13:29:55Z
dc.date.issued 2000
dc.identifier.citation Jaksic, A. B., Pejovic, M. M. and Ristic, G. S. (2000) 'Properties of latent interface-trap buildup in irradiated metal–oxide–semiconductor transistors determined by switched bias isothermal annealing experiments', Applied Physics Letters, 77(25), pp. 4220-4222. doi: 10.1063/1.1336159 en
dc.identifier.volume 77
dc.identifier.issued 25
dc.identifier.startpage 4220
dc.identifier.endpage 4222
dc.identifier.issn 0003-6951
dc.identifier.issn 1077-3118
dc.identifier.uri http://hdl.handle.net/10468/4408
dc.identifier.doi 10.1063/1.1336159
dc.description.abstract Isothermal annealing experiments with switched gate bias have been performed to determine the properties of the latent interface-trap buildup during postirradiation annealing of metal-oxide-semiconductor transistors. It has been found that a bias-independent process occurs until the start of the latent interface-trap buildup. During the buildup itself, oxide-trap charge is not permanently neutralized, but is temporarily compensated. (C) 2000 American Institute of Physics. (DOI: 10.1063/1.1336159) en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher AIP Publishing en
dc.relation.uri http://aip.scitation.org/doi/abs/10.1063/1.1336159
dc.rights © 2000 American Institute of Physics.This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. The following article appeared in Jaksic, A. B., Pejovic, M. M. and Ristic, G. S. (2000) 'Properties of latent interface-trap buildup in irradiated metal–oxide–semiconductor transistors determined by switched bias isothermal annealing experiments', Applied Physics Letters, 77(25), pp. 4220-4222 and may be found at http://aip.scitation.org/doi/abs/10.1063/1.1336159 en
dc.subject Mos devices en
dc.subject Time-dependence en
dc.subject Power vdmosfets en
dc.subject Hole traps en
dc.subject 1/f noise en
dc.subject Passivation en
dc.subject Generation en
dc.subject Hydrogen en
dc.subject Creation en
dc.subject Charge en
dc.subject Annealing en
dc.subject Transistors en
dc.subject Interfacial properties en
dc.title Properties of latent interface-trap buildup in irradiated metal-oxide-semiconductor transistors determined by switched bias isothermal annealing experiments en
dc.type Article (peer-reviewed) en
dc.internal.authorcontactother Aleksandar Jaksic, Tyndall National Institute, University College Cork, Cork, Ireland +353-21-490-3000 Email: aleksandar.jaksic@tyndall.ie en
dc.internal.availability Full text available en
dc.description.version Published Version en
dc.internal.wokid WOS:000165824200047
dc.description.status Peer reviewed en
dc.identifier.journaltitle Applied Physics Letters en
dc.internal.IRISemailaddress aleksandar.jaksic@tyndall.ie en


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