Properties of latent interface-trap buildup in irradiated metal-oxide-semiconductor transistors determined by switched bias isothermal annealing experiments

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dc.contributor.authorJaksic, Aleksandar B.
dc.contributor.authorPejovic, M. M.
dc.contributor.authorRistic, G. S.
dc.date.accessioned2017-07-28T13:29:55Z
dc.date.available2017-07-28T13:29:55Z
dc.date.issued2000
dc.description.abstractIsothermal annealing experiments with switched gate bias have been performed to determine the properties of the latent interface-trap buildup during postirradiation annealing of metal-oxide-semiconductor transistors. It has been found that a bias-independent process occurs until the start of the latent interface-trap buildup. During the buildup itself, oxide-trap charge is not permanently neutralized, but is temporarily compensated. (C) 2000 American Institute of Physics. (DOI: 10.1063/1.1336159)en
dc.description.statusPeer revieweden
dc.description.versionPublished Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationJaksic, A. B., Pejovic, M. M. and Ristic, G. S. (2000) 'Properties of latent interface-trap buildup in irradiated metal–oxide–semiconductor transistors determined by switched bias isothermal annealing experiments', Applied Physics Letters, 77(25), pp. 4220-4222. doi: 10.1063/1.1336159en
dc.identifier.doi10.1063/1.1336159
dc.identifier.endpage4222
dc.identifier.issn0003-6951
dc.identifier.issn1077-3118
dc.identifier.issued25
dc.identifier.journaltitleApplied Physics Lettersen
dc.identifier.startpage4220
dc.identifier.urihttps://hdl.handle.net/10468/4408
dc.identifier.volume77
dc.language.isoenen
dc.publisherAIP Publishingen
dc.relation.urihttp://aip.scitation.org/doi/abs/10.1063/1.1336159
dc.rights© 2000 American Institute of Physics.This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. The following article appeared in Jaksic, A. B., Pejovic, M. M. and Ristic, G. S. (2000) 'Properties of latent interface-trap buildup in irradiated metal–oxide–semiconductor transistors determined by switched bias isothermal annealing experiments', Applied Physics Letters, 77(25), pp. 4220-4222 and may be found at http://aip.scitation.org/doi/abs/10.1063/1.1336159en
dc.subjectMos devicesen
dc.subjectTime-dependenceen
dc.subjectPower vdmosfetsen
dc.subjectHole trapsen
dc.subject1/f noiseen
dc.subjectPassivationen
dc.subjectGenerationen
dc.subjectHydrogenen
dc.subjectCreationen
dc.subjectChargeen
dc.subjectAnnealingen
dc.subjectTransistorsen
dc.subjectInterfacial propertiesen
dc.titleProperties of latent interface-trap buildup in irradiated metal-oxide-semiconductor transistors determined by switched bias isothermal annealing experimentsen
dc.typeArticle (peer-reviewed)en
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