Properties of latent interface-trap buildup in irradiated metal-oxide-semiconductor transistors determined by switched bias isothermal annealing experiments
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Date
2000
Authors
Jaksic, Aleksandar B.
Pejovic, M. M.
Ristic, G. S.
Journal Title
Journal ISSN
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Publisher
AIP Publishing
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Abstract
Isothermal annealing experiments with switched gate bias have been performed to determine the properties of the latent interface-trap buildup during postirradiation annealing of metal-oxide-semiconductor transistors. It has been found that a bias-independent process occurs until the start of the latent interface-trap buildup. During the buildup itself, oxide-trap charge is not permanently neutralized, but is temporarily compensated. (C) 2000 American Institute of Physics. (DOI: 10.1063/1.1336159)
Description
Keywords
Mos devices , Time-dependence , Power vdmosfets , Hole traps , 1/f noise , Passivation , Generation , Hydrogen , Creation , Charge , Annealing , Transistors , Interfacial properties
Citation
Jaksic, A. B., Pejovic, M. M. and Ristic, G. S. (2000) 'Properties of latent interface-trap buildup in irradiated metal–oxide–semiconductor transistors determined by switched bias isothermal annealing experiments', Applied Physics Letters, 77(25), pp. 4220-4222. doi: 10.1063/1.1336159
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© 2000 American Institute of Physics.This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. The following article appeared in Jaksic, A. B., Pejovic, M. M. and Ristic, G. S. (2000) 'Properties of latent interface-trap buildup in irradiated metal–oxide–semiconductor transistors determined by switched bias isothermal annealing experiments', Applied Physics Letters, 77(25), pp. 4220-4222 and may be found at http://aip.scitation.org/doi/abs/10.1063/1.1336159