A simulation-based design method to transfer surface mount RF system to flip-chip die implementation

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dc.contributor.author Zheng, Liqiang
dc.contributor.author Rodgers, Kenneth
dc.contributor.author Mathewson, Alan
dc.contributor.author O'Flynn, Brendan
dc.contributor.author Hayes, Michael
dc.contributor.author Ó Mathúna, S. Cian
dc.date.accessioned 2011-12-07T12:29:18Z
dc.date.available 2011-12-07T12:29:18Z
dc.date.copyright 2010
dc.date.issued 2010-09-16
dc.identifier.citation Zheng, Liqiang; Rodgers, Kenneth; Mathewson, Alan; O'Flynn, Brendan; Hayes, Michael; Ó Mathúna, S. Cian, 2010. A simulation-based design method to transfer surface mount RF system to flip-chip die implementation. 3rd Electronic System-Integration Technology Conference (ESTC). Berlin, Germany 13-16 Sep. IEEE: en
dc.identifier.startpage 1 en
dc.identifier.endpage 5 en
dc.identifier.isbn 978-1-4244-8554-3
dc.identifier.isbn 978-1-4244-8553-6
dc.identifier.uri http://hdl.handle.net/10468/470
dc.identifier.doi 10.1109/ESTC.2010.5642911
dc.description.abstract The flip-chip technology is a high chip density solution to meet the demand for very large scale integration design. For wireless sensor node or some similar RF applications, due to the growing requirements for the wearable and implantable implementations, flip-chip appears to be a leading technology to realize the integration and miniaturization. In this paper, flip-chip is considered as part of the whole system to affect the RF performance. A simulation based design is presented to transfer the surface mount PCB board to the flip-chip die package for the RF applications. Models are built by Q3D Extractor to extract the equivalent circuit based on the parasitic parameters of the interconnections, for both bare die and wire-bonding technologies. All the parameters and the PCB layout and stack-up are then modeled in the essential parts' design of the flip-chip RF circuit. By implementing simulation and optimization, a flip-chip package is re-designed by the parameters given by simulation sweep. Experimental results fit the simulation well for the comparison between pre-optimization and post-optimization of the bare die package's return loss performance. This design method could generally be used to transfer any surface mount PCB to flip-chip package for the RF systems or to predict the RF specifications of a RF system using the flip-chip technology. en
dc.description.uri http://www.estc-2010.de/home/estc-2010/about-estc-2010/ en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher IEEE en
dc.relation.ispartof Electronics System Integration Technology Conferences (ESTC). Berlin, Germany, Sept 13-16, 2010
dc.rights © 2010 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. en
dc.subject Flip-chip design systems en
dc.subject PCB balun circuits en
dc.subject RF applications en
dc.subject.lcsh Integrated circuits--Design and construction en
dc.subject.lcsh Flip chip technology en
dc.title A simulation-based design method to transfer surface mount RF system to flip-chip die implementation en
dc.type Conference item en
dc.internal.authorcontactother Cian O Mathuna, Tyndall Microsystems, University College Cork, Cork, Ireland. +353-21-490-3000 Email: cian.omathuna@tyndall.ie en
dc.internal.authorcontactother Ken Rodgers, Tyndall National Institute, Lee Maltings, Prospect Row, Cork, Ireland. Email: ken.rodgers@tyndall.ie en
dc.internal.authorcontactother Alan Mathewson, Heterogeneous Systems Integration, Tyndall National Institute, Lee Maltings, Cork, Ireland. Email: alan.mathewson@tyndall.ie en
dc.internal.authorcontactother Brendan O'Flynn, Tyndall National Institute, Lee Maltings, Cork, Ireland. Email: brendan.oflynn@tyndall.ie en
dc.internal.authorcontactother Mike Hayes, Tyndall National Institute, Lee Maltings, Cork, Ireland. Email: michael.hayes@tyndall.ie en
dc.internal.availability Full text available en
dc.date.updated 2011-12-05T16:46:18Z
dc.description.version Accepted Version en
dc.internal.rssid 116535702
dc.contributor.funder Science Foundation Ireland en
dc.description.status Not peer reviewed en
dc.internal.copyrightchecked Yes Following IEEE guidelines from SHERPA RoMEO en
dc.internal.licenseacceptance Yes en
dc.internal.conferencelocation Berlin en
dc.internal.IRISemailaddress cian.omathuna@tyndall.ie en
dc.relation.project info:eu-repo/grantAgreement/SFI/SFI Centre for Science Engineering and Technology (CSET)/07/CE/I1147/IE/CSET CLARITY: Bringing Information to Life/


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