Bandwidth enhancement to continuous-time input pipeline ADCs
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Accepted Version
Date
2018
Authors
O'Hare, Daniel
Scanlan, Anthony G.
Thompson, Eric
Mullane, Brendan
Journal Title
Journal ISSN
Volume Title
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Published Version
Abstract
This paper presents design analysis and insights for a new continuous-time input pipeline (CTIP) analog-to-digital converter (ADC) architecture that has enhanced bandwidth. An all-pass filter-based analog delay in the signal path allows bandwidth extension to Nyquist signal bandwidths. A resetting integrator gain stage provides a signal path delay helping to increase the bandwidth while reducing the power cost. The noise filtering property of the resetting integrator gain stage preserves the medium resistive input benefit of CTIP ADCs. The resetting integrator allows the architecture to be implemented with a feedforward compensated op-amp using low-voltage CMOS processes. This paper has been verified by simulation results of a CTIP ADC with 1.2-V supply voltage designed in TSMC's 65-nm CMOS technology.
Description
Keywords
Analog-to-digital conversion , Antialias filter , CMOS analog integrated circuits , Continuous time , Pipeline
Citation
O’Hare, D., Scanlan, A. G., Thompson, E. and Mullane, B. (2018) 'Bandwidth enhancement to continuous-time input pipeline ADCs', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(2), pp. 404-415. doi: 10.1109/TVLSI.2017.2763129