Bandwidth enhancement to continuous-time input pipeline ADCs

Show simple item record

dc.contributor.author O'Hare, Daniel
dc.contributor.author Scanlan, Anthony G.
dc.contributor.author Thompson, Eric
dc.contributor.author Mullane, Brendan
dc.date.accessioned 2018-07-30T10:30:32Z
dc.date.available 2018-07-30T10:30:32Z
dc.date.issued 2018
dc.identifier.citation O’Hare, D., Scanlan, A. G., Thompson, E. and Mullane, B. (2018) 'Bandwidth enhancement to continuous-time input pipeline ADCs', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(2), pp. 404-415. doi: 10.1109/TVLSI.2017.2763129 en
dc.identifier.volume 26
dc.identifier.issued 2
dc.identifier.startpage 404
dc.identifier.endpage 415
dc.identifier.issn 1063-8210
dc.identifier.uri http://hdl.handle.net/10468/6522
dc.identifier.doi 10.1109/TVLSI.2017.2763129
dc.description.abstract This paper presents design analysis and insights for a new continuous-time input pipeline (CTIP) analog-to-digital converter (ADC) architecture that has enhanced bandwidth. An all-pass filter-based analog delay in the signal path allows bandwidth extension to Nyquist signal bandwidths. A resetting integrator gain stage provides a signal path delay helping to increase the bandwidth while reducing the power cost. The noise filtering property of the resetting integrator gain stage preserves the medium resistive input benefit of CTIP ADCs. The resetting integrator allows the architecture to be implemented with a feedforward compensated op-amp using low-voltage CMOS processes. This paper has been verified by simulation results of a CTIP ADC with 1.2-V supply voltage designed in TSMC's 65-nm CMOS technology. en
dc.description.sponsorship Enterprise Ireland (Innovation Partnership Project IP-2014-0293) en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) en
dc.relation.uri https://ieeexplore.ieee.org/document/8091299/
dc.rights © 2017, IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. en
dc.rights.uri http://www.ieee.org/publications_standards/publications/rights/index.html
dc.subject Analog-to-digital conversion en
dc.subject Antialias filter en
dc.subject CMOS analog integrated circuits en
dc.subject Continuous time en
dc.subject Pipeline en
dc.title Bandwidth enhancement to continuous-time input pipeline ADCs en
dc.type Article (peer-reviewed) en
dc.internal.authorcontactother Daniel O’Hare, Tyndall National Institute, University College Cork, Cork, Ireland +353-21-490-3000 Email: daniel.ohare@tyndall.ie en
dc.internal.availability Full text available en
dc.description.version Accepted Version en
dc.contributor.funder European Regional Development Fund
dc.contributor.funder Irish Government
dc.contributor.funder Enterprise Ireland
dc.description.status Peer reviewed en
dc.identifier.journaltitle IEEE Transactions on Very Large Scale Integration (VLSI) Systems en
dc.internal.IRISemailaddress daniel.ohare@tyndall.ie en


Files in this item

This item appears in the following Collection(s)

Show simple item record

This website uses cookies. By using this website, you consent to the use of cookies in accordance with the UCC Privacy and Cookies Statement. For more information about cookies and how you can disable them, visit our Privacy and Cookies statement