High-speed nested cascaded MASH Digital Delta-Sigma Modulator-based divider controller

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High-speed nested cascaded MASH Digital Delta-Sigma Modulator-based divider controller

Donnelly, Yann; Mo, Hongjia; Kennedy, Michael Peter
Date: 2018-05-04
Copyright: © 2018, IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Related: http://www.iscas2018.org/
Citation: Donnelly, Y., Mo, H. and Kennedy, M. P. (2018) ‘High-speed nested cascaded MASH Digital Delta-Sigma Modulator-based divider controller’, 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 27-30 May. doi:10.1109/ISCAS.2018.8351624
Published Version: 10.1109/ISCAS.2018.8351624

Abstract:

The MASH Digital Delta-Sigma Modulator (DDSM) based divider controller represents a speed bottleneck in state of the art commercial PLL-based fractional-N frequency synthesizers. As next generation systems require higher phase detector frequencies, there is a need to make ever faster divider controllers. This paper describes a fine-grained nested cascaded MASH DDSM which is significantly faster than state of the art divider controllers, thereby eliminating the current speed bottleneck.

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