High-speed nested cascaded MASH Digital Delta-Sigma Modulator-based divider controller
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Accepted Version
Date
2018-05-04
Authors
Donnelly, Yann
Mo, Hongjia
Kennedy, Michael Peter
Journal Title
Journal ISSN
Volume Title
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Published Version
Abstract
The MASH Digital Delta-Sigma Modulator (DDSM) based divider controller represents a speed bottleneck in state of the art commercial PLL-based fractional-N frequency synthesizers. As next generation systems require higher phase detector frequencies, there is a need to make ever faster divider controllers. This paper describes a fine-grained nested cascaded MASH DDSM which is significantly faster than state of the art divider controllers, thereby eliminating the current speed bottleneck.
Description
Keywords
Delta-sigma modulation , Multi-stage noise shaping , Clocks , Adders , Quantization , Delays , Modulation
Citation
Donnelly, Y., Mo, H. and Kennedy, M. P. (2018) ‘High-speed nested cascaded MASH Digital Delta-Sigma Modulator-based divider controller’, 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 27-30 May. doi:10.1109/ISCAS.2018.8351624
Copyright
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