High-speed nested cascaded MASH Digital Delta-Sigma Modulator-based divider controller

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dc.contributor.authorDonnelly, Yann
dc.contributor.authorMo, Hongjia
dc.contributor.authorKennedy, Michael Peter
dc.contributor.funderIrish Research Councilen
dc.contributor.funderScience Foundation Irelanden
dc.contributor.funderEnterprise Irelanden
dc.date.accessioned2018-12-18T09:56:58Z
dc.date.available2018-12-18T09:56:58Z
dc.date.issued2018-05-04
dc.description.abstractThe MASH Digital Delta-Sigma Modulator (DDSM) based divider controller represents a speed bottleneck in state of the art commercial PLL-based fractional-N frequency synthesizers. As next generation systems require higher phase detector frequencies, there is a need to make ever faster divider controllers. This paper describes a fine-grained nested cascaded MASH DDSM which is significantly faster than state of the art divider controllers, thereby eliminating the current speed bottleneck.en
dc.description.sponsorshipIrish Research Council (Grant Number GOIPG/2014/14222); Enterprise Ireland (Grant Number CC-2009-05)en
dc.description.statusPeer revieweden
dc.description.versionAccepted Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationDonnelly, Y., Mo, H. and Kennedy, M. P. (2018) ‘High-speed nested cascaded MASH Digital Delta-Sigma Modulator-based divider controller’, 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 27-30 May. doi:10.1109/ISCAS.2018.8351624en
dc.identifier.doi10.1109/ISCAS.2018.8351624
dc.identifier.endpage5en
dc.identifier.isbn978-1-5386-4881-0
dc.identifier.isbn978-1-5386-4882-7
dc.identifier.issn2379-447X
dc.identifier.startpage1en
dc.identifier.urihttps://hdl.handle.net/10468/7236
dc.language.isoenen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.relation.ispartof2018 IEEE International Symposium on Circuits and Systems (ISCAS)
dc.relation.projectinfo:eu-repo/grantAgreement/SFI/SFI Investigator Programme/13/IA/1979/IE/Advanced Frequency Synthesis Informed by Nonlinear Dynamics/en
dc.relation.projectinfo:eu-repo/grantAgreement/SFI/SFI Research Centres/13/RC/2077/IE/CONNECT: The Centre for Future Networks & Communications/en
dc.relation.urihttp://www.iscas2018.org/
dc.rights© 2018, IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.en
dc.subjectDelta-sigma modulationen
dc.subjectMulti-stage noise shapingen
dc.subjectClocksen
dc.subjectAddersen
dc.subjectQuantizationen
dc.subjectDelaysen
dc.subjectModulationen
dc.titleHigh-speed nested cascaded MASH Digital Delta-Sigma Modulator-based divider controlleren
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