Stress modelling of multi level interconnect schemes for future deep submicron device generations

Gonzales Montes DeOca, Carlos; Foley, Sean; Mathewson, Alan; Rohan, James F.

Stress modelling of multi level interconnect schemes for future deep submicron device generations

Files

9692.pdf(368.47 KB)

Accepted version

Date

2001-09

Authors

Gonzales Montes DeOca, Carlos

Foley, Sean

Mathewson, Alan

Rohan, James F.

Publisher

Springer

Published Version

10.1007/978-3-7091-6244-6_83

Abstract

Copper and low dielctric constantant (k) materials are poised to become the dominant interconnect scheme for integrated circuits for the future because of the low resistance and capacitance that they offer which can improve circuit performance by more than 30% over conventional interconnect schemes. This paper addresses the thermomechanical stresses in the Cu/Low k interconnect scheme through numerical simulation and identifies the locations of maximum stress in the structure with view to providing information on the impact that different dielectric materials have on the stress distribution in the interfaces between metals and dielectric layers.

Keywords

Titanium nitride , Copper layer , Finite element modelling simulation Thermomechanical stress , Metal barrier

Citation

Gonzales Montes De Oca , C., Foley, S., Mathewson, A. and Rohan, J. F. (2001) 'Stress Modelling of Multi Level Interconnect Schemes For Future Deep Submicron Device Generations', SISPAD 01: Simulation of Semiconductor Processes and Devices, Athens, Greece, 5-7 September, Vienna: Springer Vienna, pp. 364-367. doi: 10.1007/978-3-7091-6244-6