A 4th-order continuous-time ΔΣ modulator with improved clock jitter immunity using RTZ FIR DAC

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A 4th-order continuous-time ΔΣ modulator with improved clock jitter immunity using RTZ FIR DAC

Assom, Ian; Salgado, Gerardo; O'Hare, Daniel; O'Connell, Ivan; O'Donoghue, Keith A.
Date: 2018-12
Copyright: © 2018, IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Related: https://ieeexplore.ieee.org/document/8617899
Citation: Assom, I., Salgado, G., O'Hare, D., O'Connell, I. and O'Donoghue, K. A. (2018) 'A 4th-order continuous-time ΔΣ modulator with improved clock jitter immunity using RTZ FIR DAC', 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2018), Bordeaux, France, 9-12 December, pp. 725-728. doi: 10.1109/ICECS.2018.8617899
Published Version: 10.1109/ICECS.2018.8617899

Abstract:

This paper highlights the influence of the main feedback DAC non-idealities affecting the performance of Continuous-Time Delta-Sigma Modulators (CTDSMs) in radio receiver Internet-of-Things (IoT) applications. It proposes the combination of the Return-To-Zero (RTZ) DAC pulse and Finite-Impulse-Response (FIR) DAC to have inherent Inter-Symbol-Interference immunity and reduced clock jitter sensitivity, which is crucial to meet the strict linearity and Signal-To-Noise-Distortion-Ratio (SNDR) requirements for integrated IoT radio receivers. The proposed design is validated through MATLAB® Simulink® simulations, showing that a 4th order single-bit CTDSM with RTZ + FIR DAC can achieve an SNDR performance only 3dB below the ideal even in the presence of 4.2 ps rms of clock jitter at 24 MHz sampling frequency in a 250 kHz signal bandwidth.

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