A 2-MS/s, 11.22 ENOB, extended input range SAR ADC with improved DNL and offset calculation
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Accepted version
Date
2018-11
Authors
Asghar, Sohail
Afridi, Sohaib Saadat
Pillai, Anu
Schuler, Anita
de la Rosa José
O'Connell, Ivan
Journal Title
Journal ISSN
Volume Title
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Published Version
Abstract
A 12-bit successive approximation register analog-to-digital converter (ADC) with extended input range is presented. Employing an input sampling scaling technique, the presented ADC can digitize the signals with an input range of 3.2 V pp-d (±1.33 V REF ). The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The chip has been designed and implemented in a 0.13-μm CMOS process and demonstrates the state-of-the-art performance, featuring an SNDR of 69.3 dB and the SFDR of 79 dB without requiring any calibration. Total power consumption of the ADC is 0.9 mW, with a measured differential non-linearity of 1.2/-1.0 LSB and INL of 2.3/-2.2 LSB.
Description
Keywords
Analogue-digital conversion , CMOS integrated circuits , Comparators (circuits) , Integrated circuit design , Comparator offset compensation technique , Offset calculation , Input sampling scaling technique , Successive approximation register analog-to-digital converter , Extended Input Range SAR ADC , DNL , CMOS process , Noise figure 69.3 dB , Noise figure 79.0 dB , Power 0.9 mW , Size 0.13 mum , Capacitors , Linearity , Parasitic capacitance , Calibration , Monitoring , Analog-to-digital converters , SAR , Comparator offset , Capacitor segmentation , Feedback control system
Citation
Asghar, S., Afridi, S. S., Pillai, A., Schuler, A., Rosa, J. M. d. l. and O’Connell, I. (2018) 'A 2-MS/s, 11.22 ENOB, Extended Input Range SAR ADC With Improved DNL and Offset Calculation', IEEE Transactions on Circuits and Systems I: Regular Papers, 65(11), pp. 3628-3638. doi: 10.1109/TCSI.2018.2852761
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