4.48-GHz fractional- N frequency synthesizer with spurious-tone suppression via probability mass redistribution

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Donnelly, Yann
Kennedy, Michael Peter
Breslin, James
Tulisi, Stefano
Sanganagouda, Patil
Curtin, Ciarán
Brookes, Stephen
Shelly, Brian
Griffin, Patrick
Keaveney, Michael
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Institute of Electrical and Electronics Engineers (IEEE)
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A 4.48-GHz type-II charge pump fractional-N PLL implemented in a 0.18-μm BiCMOS process is presented. The divider controller's output is processed using a novel block, the probability mass redistributor, which statistically reconfigures the modulation noise such that fractional spurs are minimized. Measurements demonstrate in-band fractional spurs of -80 dBc. The solution, which is a drop-in modification of a conventional MASH structure, incurs a modulator area increase of 22%, and can be used in conjunction with other linearization strategies.
BiCMOS , Digital delta–sigma modulation , Frequency synthesis , Phase-lock loop , Spurs , Multi-stage noise shaping , Frequency synthesizers , Phase locked loops , Frequency modulation , Solid state circuits , Phase modulation
Donnelly, Y., Kennedy, M. P., Breslin, J., Tulisi, S., Patil, S., Curtin, C., Brookes, S., Shelly, B., Griffin, P. and Keaveney, M. (2019) '4.48-GHz Fractional- N Frequency Synthesizer With Spurious-Tone Suppression via Probability Mass Redistribution', IEEE Solid-State Circuits Letters, 2(11), pp. 264-267. doi: 10.1109/LSSC.2019.2943936
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