4.48-GHz fractional- N frequency synthesizer with spurious-tone suppression via probability mass redistribution

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dc.contributor.author Donnelly, Yann
dc.contributor.author Kennedy, Michael Peter
dc.contributor.author Breslin, James
dc.contributor.author Tulisi, Stefano
dc.contributor.author Sanganagouda, Patil
dc.contributor.author Curtin, Ciarán
dc.contributor.author Brookes, Stephen
dc.contributor.author Shelly, Brian
dc.contributor.author Griffin, Patrick
dc.contributor.author Keaveney, Michael
dc.date.accessioned 2020-02-19T16:48:18Z
dc.date.available 2020-02-19T16:48:18Z
dc.date.issued 2019-09-26
dc.identifier.citation Donnelly, Y., Kennedy, M. P., Breslin, J., Tulisi, S., Patil, S., Curtin, C., Brookes, S., Shelly, B., Griffin, P. and Keaveney, M. (2019) '4.48-GHz Fractional- N Frequency Synthesizer With Spurious-Tone Suppression via Probability Mass Redistribution', IEEE Solid-State Circuits Letters, 2(11), pp. 264-267. doi: 10.1109/LSSC.2019.2943936 en
dc.identifier.volume 2 en
dc.identifier.issued 11 en
dc.identifier.startpage 264 en
dc.identifier.endpage 267 en
dc.identifier.issn 2573-9603
dc.identifier.uri http://hdl.handle.net/10468/9672
dc.identifier.doi 10.1109/LSSC.2019.2943936 en
dc.description.abstract A 4.48-GHz type-II charge pump fractional-N PLL implemented in a 0.18-μm BiCMOS process is presented. The divider controller's output is processed using a novel block, the probability mass redistributor, which statistically reconfigures the modulation noise such that fractional spurs are minimized. Measurements demonstrate in-band fractional spurs of -80 dBc. The solution, which is a drop-in modification of a conventional MASH structure, incurs a modulator area increase of 22%, and can be used in conjunction with other linearization strategies. en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) en
dc.relation.uri https://ieeexplore.ieee.org/document/8850113
dc.rights © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. en
dc.subject BiCMOS en
dc.subject Digital delta–sigma modulation en
dc.subject Frequency synthesis en
dc.subject Phase-lock loop en
dc.subject Spurs en
dc.subject Multi-stage noise shaping en
dc.subject Frequency synthesizers en
dc.subject Phase locked loops en
dc.subject Frequency modulation en
dc.subject Solid state circuits en
dc.subject Phase modulation en
dc.title 4.48-GHz fractional- N frequency synthesizer with spurious-tone suppression via probability mass redistribution en
dc.type Article (peer-reviewed) en
dc.internal.authorcontactother Yann Donnelly, Electrical and Electronic Engineering, University College Cork, Cork, Ireland. T: +353-21-490-3000 en
dc.internal.availability Full text available en
dc.description.version Accepted Version en
dc.description.status Peer reviewed en
dc.identifier.journaltitle IEEE Solid-State Circuits Letter en

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