A parallel and pipelined implementation of a Pascal-simplex based two asset option pricer on FPGA using OpenCL

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O'Mahony, Aidan T.
Zeidan, Gil
Hanzon, Bernard
Popovici, Emanuel M.
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Institute of Electrical and Electronics Engineers (IEEE)
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With the resurgence of hardware for financial technology, several methods for accelerating financial option pricing have been investigated. This paper presents the first architecture and implementation of a two-asset option pricer based on Pascal’s simplex, which takes advantage of the parallelism and pipelining offered by FPGA technology. The theory that this architecture is constructed from is based on a recombining multinomial tree approach which in turn is a generalization of the binomial tree model. Furthermore, we show that while a significant difficulty exists in efficiently maintaining the intermediate values required for the computation, a solution exists in the form of FIFOs. Our implementation, on an Intel Stratix 10 GX FPGA, is based on the OpenCL framework and can compute 6250 two asset option prices per second for a time step of 100 and the pipelining of the option value computation show a 25 times improvement when a 50-step pipeline is created.
Finance , FPGA , OpenCL , European option , Field programmable gate arrays , Acceleration , Pricing , Simplex , Multiple assets
O'Mahony, A., Zeidan, G., Hanzon, B. and Popovici, E. (2020) ‘A parallel and pipelined implementation of a Pascal-simplex based two asset option pricer on FPGA using OpenCL’, NorCAS 2020, IEEE Nordic Circuits and Systems Conference, 27-28 October, Oslo, Norway, Virtual Conference, (6 pp).
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