On the interpretation of MOS impedance data in both series and parallel circuit topologies

Simple item page
dc.check.date2023-05-31
dc.check.infoAccess to this article is restricted until 24 months after publication by request of the publisheren
dc.contributor.authorCaruso, Enrico
dc.contributor.authorLin, Jun
dc.contributor.authorMonaghan, Scott
dc.contributor.authorCherkaoui, Karim
dc.contributor.authorFloyd, Liam
dc.contributor.authorGity, Farzan
dc.contributor.authorPalestri, Pierpaolo
dc.contributor.authorEsseni, David
dc.contributor.authorSelmi, Luca
dc.contributor.authorHurley, Paul K.
dc.contributor.funderScience Foundation Irelanden
dc.contributor.funderHorizon 2020en
dc.date.accessioned2021-06-22T11:08:09Z
dc.date.available2021-06-22T11:08:09Z
dc.date.issued2021-05-31
dc.date.updated2021-06-22T10:54:48Z
dc.description.abstractWe investigate the interplay between the series (S) and parallel (P) equivalent circuit representations of the MOS system conductance (G) and capacitance (C) in inversion. Experimental and simulated data for Si and InGaAs MOSCAPs are firstly analyzed mathematically. It is found that by interpreting the measured data in both the series and parallel mode, five independent values are obtained for the magnitude and frequency of the maxima and minima points of the −ωdCS,P/dω and GS,P/ω functions versus angular frequency (ω). The significance and application of the approach is presented and discussed.en
dc.description.statusPeer revieweden
dc.description.versionAccepted Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.articleid108098en
dc.identifier.citationCaruso, E., Lin, J., Monaghan, S., Cherkaoui, K., Floyd, L., Gity, F., Palestri, P., Esseni, D., Selmi, L. and Hurley, P. K. (2021) 'On the interpretation of MOS impedance data in both series and parallel circuit topologies', Solid-State Electronics, 185, pp. 108098 (5 pp). doi: 10.1016/j.sse.2021.108098en
dc.identifier.doi10.1016/j.sse.2021.108098en
dc.identifier.endpage5en
dc.identifier.issn0038-1101
dc.identifier.journaltitleSolid-State Electronicsen
dc.identifier.startpage1en
dc.identifier.urihttps://hdl.handle.net/10468/11472
dc.identifier.volume185en
dc.language.isoenen
dc.publisherElsevieren
dc.relation.projectinfo:eu-repo/grantAgreement/SFI/SFI Research Centres/12/RC/2278/IE/Advanced Materials and BioEngineering Research Centre (AMBER)/en
dc.relation.projectinfo:eu-repo/grantAgreement/EC/H2020::RIA/871764/EU/Cryogenic 3D Nanoelectronics/SEQUENCEen
dc.relation.urihttps://www.sciencedirect.com/science/article/pii/S003811012100143X
dc.rights© 2021 Elsevier Ltd. All rights reserved. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/en
dc.rights.urihttps://creativecommons.org/licenses/by-nc-nd/4.0/en
dc.subjectMOS characterizationen
dc.subjectParameter extractionen
dc.subjectOxide thicknessen
dc.subjectDopingen
dc.subjectMinority carrier lifetimeen
dc.subjectImpedance spectroscopyen
dc.subjectTCADen
dc.titleOn the interpretation of MOS impedance data in both series and parallel circuit topologiesen
dc.typeArticle (peer-reviewed)en
Files
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
INFOS_2021_Extended_SSE_17_05_2021-CLEAN-REV1.1.pdf
Size:
546.2 KB
Format:
Adobe Portable Document Format
Description:
Accepted version
Download
License bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
license.txt
Size:
2.71 KB
Format:
Item-specific license agreed upon to submission
Description:
Download
Collections
Tyndall National Institute - Journal Articles