Low-complexity FPGA-accelerated NN-based adaptive equalizer for 100 Gb/s IMDD PON
| dc.contributor.author | Roshanshomal, Ehsan | en |
| dc.contributor.author | Murphy, Stephen L. | en |
| dc.contributor.author | Ayat, S. Omid | en |
| dc.contributor.author | Jamali, Fariba | en |
| dc.contributor.author | Townsend, Paul D. | en |
| dc.contributor.author | Antony, Cleitus | en |
| dc.contributor.funder | Science Foundation Ireland | en |
| dc.date.accessioned | 2025-10-10T15:38:28Z | |
| dc.date.available | 2025-10-10T15:38:28Z | |
| dc.date.issued | 2025-09-03 | en |
| dc.description.abstract | We demonstrate a low-complexity, field-programable gate array (FPGA)-based adaptive neural network equalizer to mitigate nonlinear impairments caused by semiconductor optical amplifier (SOA) gain saturation in a 100 Gb/s intensity modulation with direct detection (IMDD) passive optical network (PON). The proposed equalizer employs a 32-tap feedforward neural network (FFNN) for multi-symbol detection. This approach incorporates both offline training and adaptive learning techniques to ensure real-time adaptability. To enhance FPGA efficiency, the model is quantized to an 8-bit fixed-point format, and the FFNN core is parallelized to achieve a 100 Gb/s throughput. Experimental results show a dynamic range of 27.8 dB and a sensitivity of -22.8 dBm. This approach improves real-time digital signal processing and establishes a foundation for future machine learning-based solutions in next-generation PON systems, addressing key performance challenges. | en |
| dc.description.sponsorship | Science Foundation Ireland (12/RC/2276-P2) | en |
| dc.description.status | Peer reviewed | en |
| dc.description.version | Accepted Version | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.citation | Roshanshomal, E., Murphy, S. L., Ayat, S. O., Jamali, F., Townsend, P. D. and Antony, C. (2025) 'Low-complexity FPGA-accelerated NN-based adaptive equalizer for 100 Gb/s IMDD PON', 2025 IEEE International Conference on Machine Learning for Communication and Networking (ICMLCN), Barcelona, Spain, 26-29 May 2025, pp. 1-5. https://doi.org/10.1109/ICMLCN64995.2025.11140557 | en |
| dc.identifier.doi | 10.1109/icmlcn64995.2025.11140557 | en |
| dc.identifier.endpage | 5 | en |
| dc.identifier.isbn | 979-8-3315-2042-7 | en |
| dc.identifier.isbn | 979-8-3315-2043-4 | en |
| dc.identifier.startpage | 1 | en |
| dc.identifier.uri | https://hdl.handle.net/10468/18019 | |
| dc.language.iso | en | en |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
| dc.relation.ispartof | 2025 IEEE International Conference on Machine Learning for Communication and Networking (ICMLCN), Barcelona, Spain, 26-29 May 2025 | en |
| dc.rights | © 2025, IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | en |
| dc.subject | Neural network | en |
| dc.subject | FPGA | en |
| dc.subject | Equalizer | en |
| dc.subject | Passive optical network | en |
| dc.title | Low-complexity FPGA-accelerated NN-based adaptive equalizer for 100 Gb/s IMDD PON | en |
| dc.type | Conference item | en |
| dc.type | proceedings-article | en |
