Frontiers of Cu electrodeposition and electroless plating for on-chip interconnects

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dc.contributor.authorRohan, James F.
dc.contributor.authorThompson, Damien
dc.contributor.editorKondo, Kazuo
dc.contributor.editorAkolkar, Rohan N.
dc.contributor.editorBarkey, Dale P.
dc.contributor.editorYokoi, Masayuki
dc.contributor.funderEnterprise Irelanden
dc.contributor.funderIDA Irelanden
dc.contributor.funderScience Foundation Irelanden
dc.contributor.funderCollaborative Centre for Applied Nanotechnologyen
dc.date.accessioned2019-04-02T14:12:15Z
dc.date.available2019-04-02T14:12:15Z
dc.date.issued2013-11-21
dc.date.updated2019-04-02T14:01:28Z
dc.description.abstractIn the electronics industry, interconnect is defined as a conductive connection between two or more circuit elements. It interconnects elements (transistor, resistors, etc.) on an integrated circuit or components on a printed circuit board. The main function of the interconnect is to contact the junctions and gates between device cells and input/output (I/O) signal pads. These functions require specific material properties. For performance or speed, the metallization structure should have low resistance and capacitance. For reliability, it is important to have the capability of carrying high current density, stability against thermal annealing, resistance against corrosion and good mechanical properties.en
dc.description.statusPeer revieweden
dc.description.urihttps://link.springer.com/bookseries/6331en
dc.description.versionAccepted Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationRohan, J. F. and Thompson, D. (2014) 'Frontiers of Cu Electrodeposition and Electroless Plating for On-chip Interconnects', in Kondo, K., Akolkar, R.N., Barkey, D.P. & Yokoi, M. (eds.) Copper Electrodeposition for Nanofabrication of Electronics Devices, New York, NY: Springer New York, pp. 99-113. doi: 10.1007/978-1-4614-9176-7_5en
dc.identifier.doi10.1007/978-1-4614-9176-7_5
dc.identifier.endpage113en
dc.identifier.isbn978-1-4614-9176-7
dc.identifier.startpage99en
dc.identifier.urihttps://hdl.handle.net/10468/7693
dc.language.isoenen
dc.publisherSpringeren
dc.relation.ispartofCopper Electrodeposition for Nanofabrication of Electronics Devices
dc.relation.projectinfo:eu-repo/grantAgreement/SFI/SFI Starting Investigator Research Grant (SIRG)/11/SIRG/B2111/IE/Engineering Multivalent Proteins for Regenerative Medicine (EMPoRiuM)/en
dc.relation.projectCollaborative Centre for Applied Nanotechnology, CCAN (Nano-EI project); Enterprise Ireland & IDA Ireland (grant no. CC/2009/0002)en
dc.relation.urihttps://link.springer.com/chapter/10.1007/978-1-4614-9176-7_5
dc.rights© Springer Science+Business Media New York 2014en
dc.subjectBarrier layeren
dc.subjectAtomic layer depositionen
dc.subjectSeed layeren
dc.subjectPhysical vapour depositionen
dc.subjectChemical mechanical polishingen
dc.titleFrontiers of Cu electrodeposition and electroless plating for on-chip interconnectsen
dc.typeBook chapteren
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