Dual-gate MoS2 transistors with sub-10 nm top-gate high-k dielectrics

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dc.check.date2019-06-19
dc.check.infoAccess to this article is restricted until 12 months after publication by request of the publisher.en
dc.contributor.authorBolshakov, Pavel
dc.contributor.authorKhosravi, Ava
dc.contributor.authorZhao, Peng
dc.contributor.authorHurley, Paul K.
dc.contributor.authorHinkle, Christopher L.
dc.contributor.authorWallace, Robert M.
dc.contributor.authorYoung, Chadwin D.
dc.contributor.funderNational Science Foundationen
dc.contributor.funderScience Foundation Irelanden
dc.date.accessioned2018-07-03T12:32:44Z
dc.date.available2018-07-03T12:32:44Z
dc.date.issued2018-06-19
dc.date.updated2018-07-03T12:20:26Z
dc.description.abstractHigh quality sub-10 nm high-k dielectrics are deposited on top of MoS2 and evaluated using a dual-gate field effect transistor configuration. Comparison between top-gate HfO2 and an Al2O3/HfO2 bilayer shows significant improvement in device performance due to the insertion of the thin Al2O3 layer. The results show that the Al2O3 buffer layer improves the interface quality by effectively reducing the net fixed positive oxide charge at the top-gate MoS2/high-k dielectric interface. Dual-gate sweeping, where both the top-gate and the back-gate are swept simultaneously, provides significant insight into the role of these oxide charges and improves overall device performance. Dual-gate transistors encapsulated in an Al2O3 dielectric demonstrate a near-ideal subthreshold swing of ∼60 mV/dec and a high field effect mobility of 100 cm2/V·s.en
dc.description.sponsorshipNational Science Foundation (US/Ireland R&D Partnership (UNITE) Award No. ECCS1407765)en
dc.description.statusPeer revieweden
dc.description.versionPublished Versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.articleid253502
dc.identifier.citationBolshakov, P., Khosravi, A., Zhao, P., Hurley, P. K.; Hinkle, C. L., Wallace, R. M. and Young, C. D. (2018) 'Dual-gate MoS2 transistors with sub-10 nm top-gate high-k dielectrics', Applied Physics Letters, 112, 253502 (5pp). doi:10.1063/1.5027102en
dc.identifier.doi10.1063/1.5027102
dc.identifier.issn0003-6951
dc.identifier.issn1077-3118
dc.identifier.issued25en
dc.identifier.journaltitleApplied Physics Lettersen
dc.identifier.urihttps://hdl.handle.net/10468/6407
dc.identifier.volume112en
dc.language.isoenen
dc.publisherAIP Publishingen
dc.relation.projectinfo:eu-repo/grantAgreement/SFI/SFI US Ireland R&D Partnership/13/US/I2862/IE/Understanding the Nature of Interfaces in Two Dimensional Electronic Devises (UNITE)/en
dc.rights© 2018, Article authors. This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. The following article appeared in Bolshakov, P., Khosravi, A., Zhao, P., Hurley, P. K.; Hinkle, C. L., Wallace, R. M. and Young, C. D. (2018) 'Dual-gate MoS2 transistors with sub-10 nm top-gate high-k dielectrics', Applied Physics Letters, 112, 253502 (5pp). doi:10.1063/1.5027102, and may be found at https://doi.org/10.1063/1.5027102en
dc.subjectDielectric materialsen
dc.subjectEncapsulationen
dc.subjectField effect transistorsen
dc.subjectMolybdenum compoundsen
dc.titleDual-gate MoS2 transistors with sub-10 nm top-gate high-k dielectricsen
dc.typeArticle (peer-reviewed)en
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