Power analysis of sorting algorithms on FPGA using OpenCL
O'Mahony, Aidan T.
Popovici, Emanuel M.
Institute of Electrical and Electronics Engineers (IEEE)
With the advent of big data and cloud computing, there is tremendous interest in optimised algorithms and architectures for sorting either using software or hardware. Field Programmable Gate Arrays (FPGAs) are being increasingly used in high end data servers providing a bridge between the flexibility of software and performance benefits of hardware. In this paper we look at implementations of some of the most popular sorting algorithms using OpenCL which take advantage of FPGA architecture. We evaluate these implementations in terms of power consumption which is measured using dedicated server power loggers and execution on Intel Arria 10 hardware. Our experiments show that taking advantage of software FIFOs have a significant impact on power consumption as well as requiring less hardware and memory resources.
VLSI , ASIC , FPGAs for signal processing , Energy efficiency , Field Programmable Gate Arrays (FPGAs) , Big data , Cloud computing , Acceleration , Sorting , Power consumption , Radix sort , Bitonic sort , Odd/even sort , Insertion sort
O'Mahony, A. and Popovici, E. (2018) 'Power analysis of sorting algorithms on FPGA using OpenCL', 29th Irish Signals and Systems Conference (ISSC 2018), 21-22 June, Belfast. doi: 10.1109/ISSC.2018.8585361
© 2018 European Union; © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.