Power analysis of sorting algorithms on FPGA using OpenCL

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dc.contributor.author O'Mahony, Aidan T.
dc.contributor.author Popovici, Emanuel M.
dc.date.accessioned 2018-10-25T14:42:45Z
dc.date.available 2018-10-25T14:42:45Z
dc.date.issued 2018-06-21
dc.identifier.citation O'Mahony, A. and Popovici, E. (2018) 'Power analysis of sorting algorithms on FPGA using OpenCL', 29th Irish Signals and Systems Conference (ISSC 2018), 21-22 June, Belfast. doi: 10.1109/ISSC.2018.8585361 en
dc.identifier.startpage 1 en
dc.identifier.endpage 6 en
dc.identifier.isbn 978-1-5386-6046-1
dc.identifier.uri http://hdl.handle.net/10468/7054
dc.identifier.doi 10.1109/ISSC.2018.8585361
dc.description.abstract With the advent of big data and cloud computing, there is tremendous interest in optimised algorithms and architectures for sorting either using software or hardware. Field Programmable Gate Arrays (FPGAs) are being increasingly used in high end data servers providing a bridge between the flexibility of software and performance benefits of hardware. In this paper we look at implementations of some of the most popular sorting algorithms using OpenCL which take advantage of FPGA architecture. We evaluate these implementations in terms of power consumption which is measured using dedicated server power loggers and execution on Intel Arria 10 hardware. Our experiments show that taking advantage of software FIFOs have a significant impact on power consumption as well as requiring less hardware and memory resources. en
dc.description.sponsorship Intel Corporation (Intel Programmable Solutions Group, Racktivity); Science Foundation Ireland (SFI INSIGHT Centre for Data Analytics) en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) en
dc.relation.uri https://ieeexplore.ieee.org/abstract/document/8585361 en
dc.rights © 2018 European Union; © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. en
dc.subject VLSI en
dc.subject ASIC en
dc.subject FPGAs for signal processing en
dc.subject Energy efficiency en
dc.subject Field Programmable Gate Arrays (FPGAs) en
dc.subject Big data en
dc.subject Cloud computing en
dc.subject Acceleration en
dc.subject Sorting en
dc.subject Power consumption en
dc.subject Radix sort en
dc.subject Bitonic sort en
dc.subject Odd/even sort en
dc.subject Insertion sort en
dc.title Power analysis of sorting algorithms on FPGA using OpenCL en
dc.type Conference item en
dc.internal.authorcontactother Aidan T. O'Mahony, Electrical and Electronic Engineering , University College Cork, Cork, Ireland. +353-21-490-3000 en
dc.internal.availability Full text available en
dc.description.version Accepted Version en
dc.contributor.funder Intel Corporation en
dc.contributor.funder Science Foundation Ireland en
dc.description.status Peer reviewed en
dc.internal.copyrightchecked !!CORA!! en
dc.internal.conferencelocation Belfast en
dc.internal.IRISemailaddress 103837793@umail.ucc.ie en
dc.internal.IRISemailaddress e.popovici@ucc.ie
dc.relation.project info:eu-repo/grantAgreement/SFI/SFI Research Centres/12/RC/2289/IE/INSIGHT - Irelands Big Data and Analytics Research Centre/

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