Profiling border-traps by TCAD analysis of multifrequency CV-curves in Al2O3/InGaAs stacks

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dc.contributor.author Caruso, Enrico
dc.contributor.author Lin, Jun
dc.contributor.author Burke, K. F.
dc.contributor.author Cherkaoui, Karim
dc.contributor.author Esseni, David
dc.contributor.author Gity, Farzan
dc.contributor.author Monaghan, Scott
dc.contributor.author Palestri, Pierpaolo
dc.contributor.author Hurley, Paul K.
dc.contributor.author Selmi, Luca
dc.date.accessioned 2018-11-30T12:43:20Z
dc.date.available 2018-11-30T12:43:20Z
dc.date.issued 2018-05-07
dc.identifier.citation Caruso, E., Lin, J., Burke, K. F.; Cherkaoui, K., Esseni, D., Gity, F., Monaghan, S., Palestri, P., Hurley, P. K. and Selmi, L. (2018) 'Profiling border-traps by TCAD analysis of multifrequency CV-curves in Al2O3/InGaAs stacks', Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Granada, Spain, 19-21 March. doi:10.1109/ULIS.2018.8354757 en
dc.identifier.startpage 1 en
dc.identifier.endpage 4 en
dc.identifier.issn 2472-9132
dc.identifier.uri http://hdl.handle.net/10468/7161
dc.identifier.doi 10.1109/ULIS.2018.8354757
dc.description.abstract This paper reports physics based TCAD simulations of multi-frequency C-V curves of In0.53Ga0.47As MOSCAPs including the AC response of the border traps. The calculations reproduce the experimental inversion and accumulation capacitance versus frequency, and provide a means to profile the space and energy density of states of border traps. A sensitivity analysis of the results to border traps' distribution is carried out changing the trap volume and the oxide capacitance. en
dc.description.uri https://congresos.ugr.es/eurosoi-ulis2018/ en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) en
dc.relation.ispartof Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) 2018
dc.rights © 2018, IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. en
dc.subject Capacitance en
dc.subject Electron traps en
dc.subject Gallium arsenide en
dc.subject Hole traps en
dc.subject III-V semiconductors en
dc.subject Indium compounds en
dc.subject Interface states en
dc.subject MOS capacitors en
dc.subject Technology CAD en
dc.subject Multifrequency CV-curves en
dc.subject TCAD simulations en
dc.subject Sensitivity analysis en
dc.subject Border trap profiling en
dc.subject Capacitance-voltage curves en
dc.subject MOSCAP en
dc.subject Density of states en
dc.subject Oxide capacitance en
dc.subject Al2O3/InGaAs stacks en
dc.subject Capacitance-voltage characteristics en
dc.subject Dielectrics en
dc.subject Analytical models en
dc.subject Mathematical model en
dc.subject Dielectric measurement en
dc.subject Dispersion en
dc.subject III-V compounds en
dc.subject TCAD simulation en
dc.subject Border traps en
dc.subject Parameter extraction en
dc.subject C-V en
dc.subject Trap volume en
dc.title Profiling border-traps by TCAD analysis of multifrequency CV-curves in Al2O3/InGaAs stacks en
dc.type Conference item en
dc.internal.authorcontactother Enrico Caruso, Tyndall Micronano Electronics, University College Cork, Cork, Ireland. +353-21-490-3000 Email: enrico.caruso@tyndall.ie en
dc.internal.availability Full text available en
dc.date.updated 2018-11-30T12:34:22Z
dc.description.version Accepted Version en
dc.internal.rssid 463811374
dc.contributor.funder Seventh Framework Programme en
dc.contributor.funder Horizon 2020 en
dc.description.status Not peer reviewed en
dc.internal.copyrightchecked Yes en
dc.internal.licenseacceptance Yes en
dc.internal.IRISemailaddress enrico.caruso@tyndall.ie en
dc.relation.project info:eu-repo/grantAgreement/EC/FP7::SP1::ICT/619326/EU/Technology CAD for III-V Semiconductor-based MOSFETs/III-V-MOS en
dc.relation.project info:eu-repo/grantAgreement/EC/H2020::RIA/688784/EU/Integration of III-V Nanowire Semiconductors for next Generation High Performance CMOS SOC Technologies/INSIGHT en


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