High-speed nested cascaded MASH Digital Delta-Sigma Modulator-based divider controller

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dc.contributor.author Donnelly, Yann
dc.contributor.author Mo, Hongjia
dc.contributor.author Kennedy, Michael Peter
dc.date.accessioned 2018-12-18T09:56:58Z
dc.date.available 2018-12-18T09:56:58Z
dc.date.issued 2018-05-04
dc.identifier.citation Donnelly, Y., Mo, H. and Kennedy, M. P. (2018) ‘High-speed nested cascaded MASH Digital Delta-Sigma Modulator-based divider controller’, 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 27-30 May. doi:10.1109/ISCAS.2018.8351624 en
dc.identifier.startpage 1 en
dc.identifier.endpage 5 en
dc.identifier.isbn 978-1-5386-4881-0
dc.identifier.isbn 978-1-5386-4882-7
dc.identifier.issn 2379-447X
dc.identifier.uri http://hdl.handle.net/10468/7236
dc.identifier.doi 10.1109/ISCAS.2018.8351624
dc.description.abstract The MASH Digital Delta-Sigma Modulator (DDSM) based divider controller represents a speed bottleneck in state of the art commercial PLL-based fractional-N frequency synthesizers. As next generation systems require higher phase detector frequencies, there is a need to make ever faster divider controllers. This paper describes a fine-grained nested cascaded MASH DDSM which is significantly faster than state of the art divider controllers, thereby eliminating the current speed bottleneck. en
dc.description.sponsorship Irish Research Council (Grant Number GOIPG/2014/14222); Enterprise Ireland (Grant Number CC-2009-05) en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) en
dc.relation.ispartof 2018 IEEE International Symposium on Circuits and Systems (ISCAS)
dc.relation.uri http://www.iscas2018.org/
dc.rights © 2018, IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. en
dc.subject Delta-sigma modulation en
dc.subject Multi-stage noise shaping en
dc.subject Clocks en
dc.subject Adders en
dc.subject Quantization en
dc.subject Delays en
dc.subject Modulation en
dc.title High-speed nested cascaded MASH Digital Delta-Sigma Modulator-based divider controller en
dc.internal.authorcontactother Yann Donnelly, Electrical and Electronic Engineering, University College Cork, Cork, Ireland. T: +353-21-490-3000 E: y.donnelly@umail.ucc.ie en
dc.internal.availability Full text available en
dc.description.version Accepted Version en
dc.contributor.funder Irish Research Council en
dc.contributor.funder Science Foundation Ireland en
dc.contributor.funder Enterprise Ireland en
dc.description.status Peer reviewed en
dc.relation.project info:eu-repo/grantAgreement/SFI/SFI Investigator Programme/13/IA/1979/IE/Advanced Frequency Synthesis Informed by Nonlinear Dynamics/ en
dc.relation.project info:eu-repo/grantAgreement/SFI/SFI Research Centres/13/RC/2077/IE/CONNECT: The Centre for Future Networks & Communications/ en


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