Stress modelling of multi level interconnect schemes for future deep submicron device generations

Show simple item record Gonzales Montes DeOca, Carlos Foley, Sean Mathewson, Alan Rohan, James F.
dc.contributor.editor Tsoukalas, D.
dc.contributor.editor Tsamis, C. 2019-04-02T13:41:35Z 2019-04-02T13:41:35Z 2001-09
dc.identifier.citation Gonzales Montes De Oca , C., Foley, S., Mathewson, A. and Rohan, J. F. (2001) 'Stress Modelling of Multi Level Interconnect Schemes For Future Deep Submicron Device Generations', SISPAD 01: Simulation of Semiconductor Processes and Devices, Athens, Greece, 5-7 September, Vienna: Springer Vienna, pp. 364-367. doi: 10.1007/978-3-7091-6244-6 en
dc.identifier.startpage 364 en
dc.identifier.endpage 367 en
dc.identifier.isbn 978-3-7091-7278-0
dc.identifier.doi 10.1007/978-3-7091-6244-6_83
dc.description.abstract Copper and low dielctric constantant (k) materials are poised to become the dominant interconnect scheme for integrated circuits for the future because of the low resistance and capacitance that they offer which can improve circuit performance by more than 30% over conventional interconnect schemes. This paper addresses the thermomechanical stresses in the Cu/Low k interconnect scheme through numerical simulation and identifies the locations of maximum stress in the structure with view to providing information on the impact that different dielectric materials have on the stress distribution in the interfaces between metals and dielectric layers. en
dc.description.uri en
dc.format.mimetype application/pdf en
dc.language.iso en en
dc.publisher Springer en
dc.relation.ispartof SISPAD 2001: Proceedings of the International Conference on Simulation of Semiconductor Devices and Processes
dc.rights © 2001 Springer-Verlag Wien en
dc.subject Titanium nitride en
dc.subject Copper layer en
dc.subject Finite element modelling simulation Thermomechanical stress en
dc.subject Metal barrier en
dc.title Stress modelling of multi level interconnect schemes for future deep submicron device generations en
dc.title.alternative Stress modeling of multi level interconnect schemes for future deep submicron device generations en
dc.type Conference item en
dc.internal.authorcontactother James Rohan, Tyndall Microsystems, University College Cork, Cork, Ireland. +353-21-490-3000 Email: en
dc.internal.availability Full text available en 2019-04-02T13:34:29Z
dc.description.version Accepted Version en
dc.internal.rssid 269699424
dc.description.status Peer reviewed en
dc.internal.copyrightchecked No !!CORA!! en
dc.internal.licenseacceptance Yes en
dc.internal.conferencelocation Athens, Greece en
dc.internal.IRISemailaddress en

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